Paul V. Gratz, PhD

Paul V. Gratz, Ph.D., is a Professor at Texas A&M University who has over 25 years of experience in processor design, verification, memory systems, DRAM, microelectronics, digital design, electronic design automation (EDA), storage systems, embedded hardware/software systems, and hardware cybersecurity for industry, academia and as an expert consultant.

He has served as an expert witness for several cases involving computer hardware analysis, Verilog RTL analysis, EDA tool software analysis, embedded system design, and Flash device hardware and firmware.

From 1997 to 2002, Prof. Gratz worked at Intel Corporation as a design engineer and design automation engineer, contributing to several major CPU projects. Additionally, he designed and taped out a large, novel processor in academia, which resulted in several patents and publications. He was responsible for the design of the L2 cache, on-chip and off-chip interconnection network.

Prof. Gratz earned his PhD in computer engineering from the University of Texas at Austin. He was a professor in ECEN for 15 years. His 90+ published works have appeared in top-tier publications. He also is the recipient of 13 research awards and nominations.

Areas of Expertise

Additional Expertise:

Processor Design, Verification, DRAM, Electronic Design Automation (EDA), Embedded Hardware and Software Systems, and Hardware Cybersecurity.

Areas Served

All States

Paul V. Gratz, PhD in the Social Networks

LinkedIn

Professional Experience

Consulting Work

Apple v. Rivos: October 2023 – July 2024
Expert for prosecution, Apple, in trade secret misappropriation case. Expert reports, Processor Microarchitecture analysis, Verilog RTL code analysis, C++ code analysis.

Bell Semiconductor v. Synopsys: April 2023 – February 2024
Expert for prosecution, Bell Semi, in patent infringement case. Generated expert witness reports on software similarity between tools from different vendors in EDA tools case.

Lenovo Group Ltd.: June 2022 – August 2022
Consulted on the design of a prefetching engine for a new System-on-Chip processor to be manufactured by Lenovo. Prefetching engine based on my prior academic work, “Path Confidence based Lookahead Prefetching”, published in MICRO'2016.

Zeku Inc.: June 2021 – Aug. 2022
Consulted on the design of a prefetching engine for a new System-on-Chip processor to be manufactured by Oppo. Prefetching engine based on my prior academic work, “Path Confidence based Lookahead Prefetching”, published in MICRO'2016.

Profectus v. Google: Sept. 2020 – June 2021
Expert for defense, Google, in patent suit. Case involved Profectus' claim of patent infringement by Google with respect to the Google Nest Home Hub versus Profectus' patents on digital picture frames. Researched and developed expert reports.

Huawei v. CNEX: Sept. 2018 – June 2019
Expert for defense, CNEX/Ronnie Huang, in trade secrets case. Case involved Huawei's claim that former employee, Ronnie Huang, misappropriated trade secrets involving a Flash SSD technologies. Researched and developed expert reports.

Full Time Positions
Texas A&M University, College Station, Texas USA
Professor: 2021 – present
Associate Professor: 2015 – 2021
Assistant Professor: 2009 – 2015
Department of Electrical and Computer Engineering
Research Interests: Computer Architecture, On-chip interconnection networks, High performance multicore and distributed computer architectures, Processor memory systems.

Intel Corp., Austin, Texas USA
Design Automation Engineer: 2000 – 2002
Developed and supported RTL database build tools for full-chip verilog model using Synopsys VCS. Developed and supported validation test-running tools to support massive parallel runs of tests in a batched network environment.

Intel Corp., Chandler, Arizona USA
Design Engineer: 1997 – 2000
Developed and supported logic verification tools for the Itanium project. Performed logic verification on the Itanium full chip model. Uncovered initialization problems by comparing schematics and RTL using logic validation tools. Circuit design of the Itanium CPU ID fuse unit. Performance evaluation of the Strongarm 1100 microprocessor. Logic verification on the debug (DBG), performance monitoring (PMU), and in-test circuit (ITC) units of the Itanium processor. Architecture validation on an i960 derivative microprocessor.

Legal Experience & Services

Apple v. Rivos: October 2023 – July 2024
Expert for prosecution, Apple, in trade secret misappropriation case. Expert reports, Processor Microarchitecture analysis, Verilog RTL code analysis, C++ code analysis.

Bell Semiconductor v. Synopsys: April 2023 – February 2024
Expert for prosecution, Bell Semi, in patent infringement case. Generated expert witness reports on software similarity between tools from different vendors in EDA tools case.

Lenovo Group Ltd.: June 2022 – August 2022
Consulted on the design of a prefetching engine for a new System-on-Chip processor to be manufactured by Lenovo. Prefetching engine based on my prior academic work, “Path Confidence based Lookahead Prefetching”, published in MICRO'2016.

Zeku Inc.: June 2021 – Aug. 2022
Consulted on the design of a prefetching engine for a new System-on-Chip processor to be manufactured by Oppo. Prefetching engine based on my prior academic work, “Path Confidence based Lookahead Prefetching”, published in MICRO'2016.

Profectus v. Google: Sept. 2020 – June 2021
Expert for defense, Google, in patent suit. Case involved Profectus' claim of patent infringement by Google with respect to the Google Nest Home Hub versus Profectus' patents on digital picture frames. Researched and developed expert reports.

Huawei v. CNEX: Sept. 2018 – June 2019
Expert for defense, CNEX/Ronnie Huang, in trade secrets case. Case involved Huawei's claim that former employee, Ronnie Huang, misappropriated trade secrets involving a Flash SSD technologies. Researched and developed expert reports.

Affiliations

Senior Member, IEEE (Computer Society)
Member, ACM (SIGARCH)

Awards & Honors

Research Honors:

- ECEN Departmental Faculty Fellow, 2024-2025, Electrical and Computer Engineering Department, Texas A&M University.
- Best Paper Nomination (5/70, top 5.7%) for the paper “Aiding Microprocessor Performance Validation with Machine Learning”, 2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), May 2024.
- Best Paper Nomination (6/379, top 1.6%), for the paper “SEEC: Stochastic Escape Express Channel”, International Conference for High Performance Computing, Networking, Storage and Analysis (SC21), November 2021.
- IEEE Micro's Top Picks, for the paper “Synchronized Progress in Interconnection Networks (SPIN) : A New Theory for Deadlock Freedom”, April 2019.
- Best Paper Nomination (5/283, top 1.7%), “Path Confidence based Lookahead Prefetching”, The 49th ACM/IEEE International Symposium on Microarchitecture (MICRO), Oct. 2016.
- Best Paper Nomination (5/269, top 1.9%), “Energy-Efficient Implementations of GF(p)and GF(2m )Elliptic Curve Cryptography”, The 33rd IEEE International Conference on Computer Design (ICCD), Oct. 2015.
- Best Paper Nomination (7/804, top .8%), “A Control-Theoretic Approach for Energy Efficient CPU-GPU Subsystem in Mobile Platforms”, The 52th ACM/EDAC/IEEE The Design Automation Conference (DAC), June. 2015.
- Best Paper Nomination (5/279, top 1.8%), “B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors”, The 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Dec. 2014.
- Best Paper Award, “Stochastic Pre-Classification for SDN Data Plane Matching.” The 22nd IEEE International Conference on Network Protocols (ICNP) CoolSDN Workshop, Oct. 2014.
- HiPEAC Paper Award, “Up By Their Bootstraps: Online Learning in Artificial Neural Networks for CMP Uncore Power Management”, in The 20th IEEE International Symposium on High Performance Computer Architecture (HPCA), HiPEAC Network of Excellence, Feb. 2014.
- HiPEAC Paper Award, “Use It Or Lose It: Wear-out and Lifetime in Future Chip Multiprocessors”, in The 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013, HiPEAC Network of Excellence, Dec. 2013.
- Best Paper Nomination, “In-Network Monitoring and Control Policy for DVFS of CMP Networks-On-Chip and Last Level Caches”, NOCS 2012.
- Best papers of IEEE Computer Architecture Letters in 2011, “B-Fetch:Branch Prediction Directed Prefetching for In-Order Processors”, IEEE Computer Architecture Letters, Jan. 2012.
- Best Paper Award, “An Evaluation of the TRIPS Computer System”, ASPLOS 2009.

Teaching Honors:

- College of Engineering Excellence in Teaching Award, 2017, Texas A&M University, College of Engineering.
- 2016 Distinguished Achievement Award in Teaching - College Level, Texas A&M Association of Former Students.
- Teaching Excellence Award, Texas A&M University System, Teaching Excellence Award Program - Top 5%, Spring 2010.

Publications

Published >90 works in top venues, receiving 13 research awards and nominations.

For a full list, see my full CV:
https://www.dropbox.com/scl/fi/d4fhy9ej229uyzg3wq2ri/pgratz_cv_full.pdf?rlkey=rrs6qu7tpvbr6jc0853iwyg72&st=az4kudye&dl=1

or my google scholar page:
https://scholar.google.com/citations?user=O9teRZsAAAAJ&hl=en

Education

The University of Texas, Austin, Texas USA
Ph.D., Electrical and Computer Engineering, December 2008
- Dissertation Topic: Network-On-Chip Implementation and Performance Improvement Through Workload Characterization and Congestion Awareness.
- Dissertation Advisor: Dr. Stephen W. Keckler.
- Area of Study: Computer Architecture, Computer Engineering.

The University of Florida, Gainesville, Florida USA
M.S., Electrical and Computer Engineering, August 1997
- Area of Study: Digital Signal Processing.

B.S., Electrical and Computer Engineering, August 1994
- Physics Minor.